Production Socket

  1. Particle Interconnect Package
  2. Lead frame
  3. BGA
  4. Gull wing lead frame
  5. Chip sockets
  6. J-lead
  7. Removable die MCM
  8. Controlled impedance to lead of package / die pad
  9. Test results

Particle Interconnect Package

Particle Interconnect Package (PIP)

Advanced low-cost minimal IC package.

QFP 132 lead, 0.012" pitch OLB (Outer Lead Bond). Leadframe / Chip-On-Board socket & carrier.
  • 0.001"-0.005" flex/rigid board with flip chip attached topside (heat up/electrical down) {3 μ line & space on 3 μ flex obtainable at special labs}
  • Board acts as probe card/burn-in socket/final package, only bad die are thrown away at assembly.
  • Leads completely supported yet flexible and damage resistant.
  • Outer Lead Bond (OLB) attachment by conventional heated solder reflow method or non-heated Particle Interconnect methods.
  • Automatic or manual placement even with finest pitches.
  • Controlled impedance routing from OLB to die pad in either single or multi-layer PCB.
  • Lower cost than etched/stamped leadframes or conventional flip chip techniques.

Lead frame

Particle Interconnect lead frame package

Solder bumped chip (ILB) on Particle Interconnect lead frame (OLB). Particle Interconnect bumped chip (ILB) on Particle Interconnect lead frame (OLB).

Testing bumped chip on Particle Interconnect leadframe

BGA

Particle Interconnect seasaw BGA socket

BeCu spring material with Particle Interconnect bumps on opposite sides of opposite ends of beam.

Beam bent against ball

Magnified 200X.

Particle Interconnect piercing SDRAM DDR1 package balls

Particle Interconnect - Sandia Lab Known Good Die (KGD)

Known-Good-Die probe/burn-in. Proof of removable die MCM-L/D/C.

0 failures, 11 runs shown above. Particle Interconnect surface mount BGA socket.
Particle Interconnect - Sandia mBGA interposer schematic. Sandia mBGA interposer

Gull wing lead frame

RF SOIC

Controlled Impedance RF SOIC package and lead coplanarity verification Load Boards.

G-TEK Load Board with active components,
50 mil pitch, 14 lead RF SOIC
TEMM-10 Load Board with active components,
50 mil Pitch, 28 Lead RF SOIC

Alternative Particle Interconnect lead frame with holddown

Removable single unit - proof of concept.

0.025" pitch, 196 lead, ceramic QFP. 0.020" pitch, 256 lead, ceramic QFP.

Chip sockets

Particle Interconnect - MMS - TI - HP bare die probe

Proof of removable Known-Good-Die. Note single layer of particle on pad.

IEEE Transactions on Components, Packaging, And Manufacturing Technology

A Bare-Chip Probe for High I/O, High Speed Testing

Alan Barber, Keunmyung Lee, and Hannsjorg Obermaier

HPL-94-18

J-lead

Particle Interconnect PLCC universal test socket

Nesting multiple packages in one design.

0.050" pitch, 20-84 lead with coplanar verification built-in.

Removable die MCM

Removable die Multichip Module - L/D/C

  • Socket with heat sink.
  • (a) heat sink, (b) precisor, (c) bumped-die socket. (Dielectric web material not shown.)
  • 0.004" Particle Interconnect bumps (red & blue color) on BeCu (gold color) create Particle Interconnect bridges with 0.004" travel.
Removable die MCM Louver contact

Controlled impedance to lead of package / die pad

Controlled impedance to lead of package

Schematic for controlled impedance socket. Surface of PLCC J-Lead after 30,000 insertions. Surface finish of lead passed steam aging test.

Controlled impedance socket

44 pin controlled impedance Particle Interconnect PLCC socket or interposer with singulate leads. Decoupling capacitors are within 0.100" of PLCC pad.

Printed circuit board layout Mechanical hold down

Circuit layout for controlled impedance socket

D.U.T. board layout use for TDR measurement. The traces are narrowed to compensate for Z0 change due to devices present in the socket.

TDR of controlled impedance Particle Interconnect socket (interposer) on load board

Impedance =
41.5 Ω
ρ = - 9.258 %
Distance = 90.47 mm
Cursor at 0.6036 ns from reference plane
Impedance =
57.2 Ω
ρ = 6.791 %
Distance = 100.9 mm
Cursor at 0.6736 ns from reference plane
Reference plane = 23.7844 ns
Channel 1 = 200.0 mV/div Offset = 4.075 Volts
Timebase = 0.1 ns/div Delay = 24.1920 ns (Shown on graph)
Start = 24.5432 ns, Stop = 24.5474 ns, Δ T = 0.0042 ns
  1. Demonstrated controlled impedance connector from contactor board to mother board using Particle Interconnect with impedance tolerance of 50 Ω ± 1 Ω.
  2. Controlled impedance of J-lead going to package.
  3. Compensation (Point 2 on graph) to neutralize internal inductance and capacitance of PLCC package (Point 3 on graph).
  4. Particle Interconnect is 10 times better than SMA connector (Point 1 on graph).
  5. Additional work by MMS, TI, and HP.

Test results

Particle Interconnect contact resistance vs. contact force

Gold probe to top side Particle Interconnect

Particle Interconnect's very low resistance results in higher current capacity.

Particle Interconnect array top side Particle Interconnect bottom side close up

Particle Interconnect planarity and accuracy

Following picture demonstrates planarity of pads and accuracy of alignment of particles on pads.

PCB traces with pads Close up

Note sharp corners of the particles that make electrical contact at very low pressure to form a temparory bond. Solder would wick into spaces between the particles during reflowing to form perament bond.

Cross-section of the Particle Interconnect (PI) pad shows planarity of a single pad as well as planarity to adjacent pad. Close-up of PI pads shows controlled stacking of particles to a desired height with clearance between individual particles.